There are many types of MOSFET biasing methods such as zero bias, fixed bias, self bias, voltage divider bias, two supply bias and current source bias. FET transistors can either be biased in ohmic or active region(linear region). If the purpose of the FET is to use it as an amplifier then it is biased in the active region. To bias depletion MOSFET in either depletion mode or enhancement mode in the active region we can use either self bias, voltage divider bias or the two supply bias. Here voltage divider biasing of depletion MOSFET is illustrated with worked out example calculation.
Circuit & Operation
The following shows the circuit diagram of depletion MOSFET biased using voltage divider biasing.
Choose bias point
To bias the circuit we have to select the operating point in the active region. The following shows the location of the bias point Q in the active region.
\(V_{DSQ}\) = 4V, \(I_{DQ}\) = 3.62mA
Calculate gate to source voltage
After setting the drain current we can know the gate to source voltage required so that \(I_{DQ}\) = 3.62mA. The gate to source voltage relation to drain current is given by the Shockley equation.
\(I_D=I_{DSS} (1- \frac{V_{GS}}{V_{GS(off)}})^2\)
which can be resolved to,
\( V_{GS}= V_{GS(off)}(1- \sqrt{\frac{I_{DQ}}{I_{DSS}}})\)
From the graph above or the datasheet we have,
\( V_{GS(off)}=2V\) and \( I_{DSS}=2.33mA\)
Therefore,
\( V_{GS}= 2V(1- \sqrt{\frac{3.62mA}{2.33mA}}) \)
that is, \( V_{GS}= 0.49V\)
Choose gate voltage and source voltage
The gate voltage and the source voltage can be chosen equal to the gate to source voltage.
\(V_G = V_D = V_{GS} = 0.49V\)
Calculate voltage divider resistors
Knowing the gate voltage we can then determine the voltage divider resistor R1 and R2.
We have,
\(V_G = \frac{R_2}{R_1+R_2}V_{DD}\)
Rearranging,
\(R_2 = \frac{V_G}{V_{DD}-V_G}R_1\)
or, \(R_2 = \frac{V_G}{V_{DD}-V_G}R_1\)
Let \(R_1=10k\Omega\)
then, \(R_2 = \frac{0.49V}{5V-0.49V}10k\Omega\)
that is, \(R_2 = 1k\Omega\)
Calculate source resistor
The source voltage is selected equal to gate to source voltage \(V_{GS}\),
\(V_S = V_{GS} = 0.49V\)
Then, the drain resistor is,
\(R_S = \frac{V_S}{I_D}\)
or, \(R_S = \frac{0.49V}{3.62mA }\)
that is, \(R_S \simeq 135 \Omega\)Calculate drain resistor
The drain resistor is,
\(R_D = \frac{V_{DD}- V_D}{I_D}\)
or, \(R_D = \frac{5V-0.49V}{3.62mA }=\frac{4.51V}{3.62mA }\)
that is, \(R_D \simeq 1.2k\Omega\)
Calculate input/output impedance
The input impedance is due to the voltage divider circuit is,
\(Z_i \simeq R_1 || R_2 = \frac{R_1 R_2}{R_1+R_2}\)
or, \(Z_i \simeq R_1 || R_2 = \frac{1k\Omega \times 10k\Omega}{1k\Omega+10k\Omega}\)
that is, \(Z_i \simeq 909\Omega\)
The output impedance is,
\(Z_o \simeq R_D\)
that is, \(Z_o \simeq 1.2k\Omega\)
Calculate coupling capacitor
The input coupling capacitor is,
\(C_1 = \frac{1}{2 \pi f (0.1) Z_i}\)
or, \(C_1 = \frac{1}{2 \pi (1kHz) (0.1) (909\Omega)}\)
that is, \(C_1 = 1.75 \mu F\)
The output coupling capacitor is,
\(C_2 = \frac{1}{2 \pi f (0.1) Z_o}\)
or, \(C_2 = \frac{1}{2 \pi (1kHz) (0.1) (1.2k\Omega)}\)
that is, \(C_2 = 1.32 \mu F\)
Result
The following is the completed voltage divider biased depletion MOSFET amplifier.
When the input signal is 100mV amplitdue and frequency is 1kHz then the input and output waveform as shown in oscilloscope is shown below.
Recommendation
The following are recommended tutorials:
- How to design JFET source follower?
- How to design Common Gate JFET Amplifier
- How to design common source JFET Amplifier
- Comparison of BJT, JFET, D-MOSFET, E-MOSFET construction and operation
