Here JFET(Junction Field Effect Transistor) amplifier design in common source configuration with voltage divider biasing method is illustrated in this tutorial. First the operation of a common source JFET amplifier circuit is explained. Then it is explained how to determine gate to source voltage and drain current which is required to bias the transistor. The voltage divider at the gate is used to set the required gate to source voltage. After that the drain resistor and the source resistors are determined by using the drain current calculated for the operating point. Then the coupling capacitors values are calculated which requires first the calculation of the input and output impedance. Finally JFET amplifier voltage gain calculation is shown.
The JFET amplifier circuit in common source configuration is shown below.
JFET amplifier operation
The input signal Vin enters the JFET amplifier via the input coupling capacitor Cc1. The amplifier is biased using voltage divider bias. In voltage divider bias, the resistors R1 and R2 are used to create a gate voltage bias. The voltage divider bias is such that the gate to source voltage is reversed biased. The input signal enters the gate and due to square law dependence the output signal at the drain is an amplified version of the input signal. The amplified output signal appears in the load resistor RL via the output coupling capacitor Cc2. The source resistor Rs is bypassed by the bypass capacitor Cb.
In this example, we will use the 2N5459 N channel JFET. The power supply used is \(V_{DD}=5V\). To bias the JFET amplifier we need to perform first DC analysis. In this the capacitors are opened and the resistor values are calculated.
How to calculate the resistor value to bias the JFET using voltage divider bias was shown and explained in details in the tutorial JFET Biasing Worked Out Example Calculation.
First we will determine gate to source voltage and then we know what gate bias is required. Once the gate bias voltage is known we will determine the voltage divider resistor values R1 and R2. Then we will determine the drain current for the given gate to source voltage. After obtaining the drain current we can calculate the source and drain resistor values.
Determining gate to source voltage \(V_{GS}\)
For amplifier design purpose we select the operating point or Q-point such that there is maximum swing for the input and output signal. For this we need to determine the gate to source voltage and the drain current. Here it means that the gate to source \(V_{GS}\) is selected in the middle of 0V and \(-V_{GS(off)}\).
That is,
\(V_{GS} = \frac{V_{GS(off)}}{2}=\frac{V_P}{2}\)
where \(V_P\) is the pinch-off voltage.
The pinch off voltage \(V_P\) can be determined from the JFET datasheet or the drain curve. Below is the drain curve for the 2N5459 JFET plotted in Proteus software.
To learn how to plot drain graph in Proteus Software see the tutorial Import spice model in Proteus and draw JFET drain curve.From the above graph, pinch off voltage is \(V_P=1.2V\).
Therefore the gate to source voltage \(V_{GS}\) for mid-point bias is,
\(V_{GS} = \frac{1.2V}{2}=0.6V\)
Determining voltage divider resistors
To reverse bias the gate to source voltage, we will set the voltage divider bias voltage of the same magnitude, that is \(V_G=0.6V\). The gate voltage set by the voltage divider circuit is,
\(V_G = (\frac{R_2}{R_1+R_2}) V_{DD}\)
Choosing \(R_2=1k\Omega\), we have,
\(R_1=(\frac{5V-0.6V}{0.6}) 1k\Omega \)
therefore, \(R_1=7.33 k\Omega \)
Determining drain current \(I_D\)
To calculate the drain current we can either use the transconductance equation or the Shockley equation, calculate graphically using transconductance graph or using the drain curve.
For gate to source voltage of -0.6V, if we use the Shockley equation the drain current turns out to be 2.5mA. If we use the drain curve above then the drain current turns out to be 1.6mA. In this tutorial we will use the drain current obtained from drain graph, that is we will use drain current of 1.5mA. This is because in Proteus the simulation result turns out to be correct using the drain curve. This is in turn due to the fact that the spice model of 2N5459 is used in Proteus Software and we want to illustrate calculated value in the simulated circuit.
Determining source resistor \(R_S\)
After knowing the drain current \(I_D=1.6mA\) we can determine the value for source resistor \(R_S\) using the following equation,
\(V_{GS}=V_G-V_S\)
or, \(V_S=V_G-V_{GS}\)
or, \(V_S=0.6V-(-0.6V)=1.2V\)
that is, \(R_S = \frac{V_S}{I_D}=\frac{1.2V}{1.6mA}=750\Omega\)
Determining drain resistor \(R_D\)
We can determine the value for drain resistor \(R_D\) using the following equation,
\(V_{DD}=V_D+I_D R_D\)
Rearranging for drain resistor,
\(R_D = \frac{V_{DD}-V_D}{I_D}\)
Let the drain voltage \(V_D\) =2.5V, then
or, \(R_D = \frac{5V-2.5V}{1.6mA}\)
that is, \(R_D = 1.56 k\Omega\)
From this DC analysis the circuit with calculated values is shown below.
Next we add the coupling and bypass capacitors, add a 10KOhm load resistor. Apply an input sine wave signal of amplitude 100mV and frequency of 1KHz.
Determining coupling and bypass capacitor
The frequency of the input signal is 1KHz. To calculate the input coupling capacitor \(C_{c1}\) we need to find out the input impedance \(Z_{in}\). The input impedance is,
\(Z_{in}= R_1 || R_2\)
which results into,
\(Z_{in} = 7.33 k\Omega || 1 k\Omega = 880 \Omega\)
And the input coupling capacitor \(C_{c1}\) is,
\(C_{c1}=\frac{1}{2 \pi (f) (0.1) (Z_{in})}\)
This formula is explained in the tutorial How to bias a BJT using voltage divider biasing.
\(C_{c1}=\frac{1}{2 \pi (1kHz) (0.1) (880 \Omega)} = 1.8 \mu F\)
The output coupling capacitor is calculated using the formula,
\(C_{c2}=\frac{1}{2 \pi (f) (0.1) (Z_{out})}\)
where the output impedance is,
\(Z_{out}= R_D\)
Hence,
\(C_{c2}=\frac{1}{2 \pi (f) (0.1) (R_D)}= \frac{1}{2 \pi (1 kHz) (0.1) (1.56 k\Omega)}\)
that is, \(C_{c2}=1 \mu F\)
Finally, the bypass capacitor is calculated using the following formula,
\(C_{b}=\frac{1}{2 \pi (f) (0.1) (R_S)}\frac{1}{2 \pi (1 kHz) (0.1) (750 \Omega)}\)
that is, \(C_{b}=2.12 \mu F\)
Thus the JFET amplifier circuit diagram with calculated capacitor values is as follows,
The following shows the input and output signal from the JFET amplifier circuit.
This is obtained from the oscilloscope as shown below.
JFET Amplifier Gain
From the above waveform graph we can estimate the gain obtained the designed JFET amplifier.
\(A_v = \frac{V_{out}}{V_{out}}= \frac{15div \times 0.1V}{4div \times 0.1V}=3.75\)
Thus this designed JFET amplifier has a voltage gain of 3.75.
The formula for JFET amplifier gain is,
\(A_v = g_m r_d\)
where, \(g_m\) is the transconductance of the JFET and \(r_d\) is the ac drain resistor.
The ac drain resistor \(r_d\) is calculated by,
\(r_d=R_D || R_L\)
which gives, \(r_d=R_D || R_L=1.56 k\Omega || 10 k\Omega\)
that is, \(r_d=1349.5\Omega\)
The formula for calculating transconductance \(g_m\) is,
\(g_m=\frac{i_d}{v_{gs}}\)
where \(i_d\) is the ac drain current and \(v_{gs}\) is the ac gate to source voltage.
The value of transconductance \(g_m\) is specified in the JFET datasheet. For 2N5459 JFET the minimum and maximum transconductance \(g_m\) is 2000uS and 6000uS.
So in this way we can design a JFET amplifier with common source configuration and using voltage divider biasing. There are other methods of biasing JFET see below.
- JFET Current Source Bias Worked Out Example
- JFET with Two-Supply Source Bias
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